ULA Decapped!

In July 2018, Lance Ewing (Dreamseal) secured the de-capping of an actual Oric ULA. See this posting for details

Six weeks of fairly intensive reverse-engineering, drawing and documenting later, we finally have access to the complete schematics, documentation and simulation of the ULA.

Download

All images and explanatory diagrams/pictures derived from the DATEL files can be viewed and downloaded below.

Mike Connors: Dieshot

Original die-shot and size reduced versions

• README file/credits/notes
• Full size (24k x 24k pixels) (** 100MB **)
• Reduced size (8k x 8k pixels) (19MB)
• Reduced size (4k x 4k pixels) (7MB)

MJB Guide Pictures

Modified images (mostly from the 8k and 4k resolution die-shot) to highlight and mark features.

• Location of logic cells and I/O Pin areas (areas in use highlighted in colour) (18MB)
• One logic cell (87KB)
• One unused logic cell (278KB)


• Output pin driver (on top, bottom pins) (487KB)
• Output pin driver (on left, right pins) (588KB)
• Output pin pre-driver (on left, right pins only) (369KB)


• Input pin (R, D location) (1) (378KB)
• Input pin (R, D location) (2) (649KB)
• Input pin driver 2nd stage, medium/medium FETs (316KB)
• Input pin driver 2nd stage, large/small FETs (433KB)

After completing the schematics and verilog processing, I was able to go back and produce this image ...

• Activity map of functional blocks (2.5MB)
• Animated version of the functional blocks (YouTube, from HD to 2160p)

MJB Documentation/Schematics

These Eagle schematics include all the general structures, and the specific circuits of the entire ULA, and replace all the earlier partial schematics posted here

• Full documentation and schematics (105 page PDF) (Updated 4th March 2020) (16MB)
• Schematics only (18 page PDF) (Updated 4th March 2020) (2.6MB)

Logisim

A complete and accurate logisim simulation of the ULA is now available, which closely follows the Eagle schematics

A number of diagnostic/monitoring points are included to watch the ULA in action, along with memory images to load to test the ULA operation.

• Logisim 2.7.1 simulation and images (ZIP) (37KB)

Verilog Files

The original verilog files from DATEL (a raw transistor list, and an almost complete list of gates), plus my fully organized, corrected and annotated version, are in the following ZIP file. This is the underlying data that was used to produce the EagleCAD schematics

• Verilog files (ZIP) (136KB)

Errata

Since originally publishing these PDFs in August 2018 :-

March 2020: Thanks to zxMarce for spotting a drawing/connection error on P12 (Attribute registers). Also, some minor corrections/tidy-ups had been added to the schematics from the Logisim testing phase, which may not have made it into both versions of the schematics above, now updated and in-sync.

October 2024: On page 51 of the Unofficial ULA guide.pdf, in the section "the following master timing signals" ... the table entry "NOT 339 (CAS)" should be labelled as the gate "NAND 339 (CAS)"

November 2024: On page 58 of the Unofficial ULA guide.pdf, in the section "Further, NOR 570/NOT 679 ... " it should read "adding a further offset of 128 (0x80)" (Thanks, Edvard!)

November 2024: On page 53 of the Unofficial ULA guide.pdf, in the section "This counter counts from 0 to 64 ..." should of course read "counts from 0 to 63 across ..."