ULA Decapped!

In July 2018, Lance Ewing (Dreamseal) secured the de-capping of an actual Oric ULA. See this posting for details

Six weeks of fairly intensive reverse-engineering, drawing and documenting later, we finally have access to the complete schematics, documentation and simulation of the ULA.


All images and explanatory diagrams/pictures derived from the DATEL files can be viewed and downloaded below.

Mike Connors: Dieshot

Original die-shot and size reduced versions

MJB Guide Pictures

Modified images (mostly from the 8k and 4k resolution die-shot) to highlight and mark features.

MJB Documentation/Schematics

These Eagle schematics include all the general structures, and the specific circuits of the entire ULA, and replace all the earlier partial schematics posted here


A complete and accurate logisim simulation of the ULA is now available, which closely follows the Eagle schematics

A number of diagnostic/monitoring points are included to watch the ULA in action, along with memory images to load to test the ULA operation.

Verilog Files

The original verilog files from DATEL (a raw transistor list, and an almost complete list of gates), plus my fully organized, corrected and annotated version, are in the following ZIP file. This is the underlying data that was used to produce the EagleCAD schematics


Since originally publishing these PDFs in August 2018 :-

March 2020: Thanks to zxMarce for spotting a drawing/connection error on P12 (Attribute registers). Also, some minor corrections/tidy-ups had been added to the schematics from the Logisim testing phase, which may not have made it into both versions of the schematics above, now updated and in-sync.

Source, documentation and pictures © 2009-2019 Mike Brown. Visit the website at http://oric.signal11.org.uk for the latest version and contact details.